The present invention pertains to the field of memory devices. More particularly, this invention relates to the art of sequential burst read operations in nonvolatile memory.
Advances in computer technology have led to increasingly faster microprocessors. These faster microprocessors are capable of running increasingly larger software applications, which require faster, higher capacity memory devices. At the same time, the trend in computer technology is toward smaller, lighter, and less expensive computers. When selecting a memory device, computer designers often have to trade speed for size, cost, or storage density. A wide variety of memory devices, each with certain strengths and weaknesses, are available. Among these memory devices, flash memory has proven to be particularly useful.
Although the write and erase operations in flash memory are comparatively long, the nonvolatility and rewritability of flash memory are desirable features for a number of applications. For example, using flash to store a computer system""s Basic Input Output system (BIOS) and boot code permits the user to update the BIOS without having to replace the storage medium. Because flash memory read operations are much faster than write and erase operations, flash memory is also useful for storing xe2x80x9cROMablexe2x80x9d (i.e. read only), or xe2x80x9cread mostlyxe2x80x9d files. For example, operating system and application files can be divided up into ROM-able and read/write portions. The ROMable portions can be executed directly from flash memory, rather than waiting for the files to be loaded from hard disk to random access memory (RAM).
Even in ROMable, or infrequently updated applications, flash presents certain challenges. For instance, a flash memory read operation is typically asynchronous, meaning that data is read out of flash memory a set time after an address is provided. In other words, data is not provided in response to a clock signal. So, if the clock rate of a high speed bus connected to a flash memory is running faster than the access time of the flash memory, every memory access could introduce wait states on the high speed bus. Thus, a burst read operation might result in a wait state for each address read.
One approach to this problem is to perform a page read in synchronous mode. Instead of reading one byte or word of data for each address, a page of data is read at a time. Each page of data includes a number of words of data. The words of data are buffered and provided to the bus synchronously, one word at a time. By reading data a page at a time, wait states are only incurred once every page of data rather than once every word or byte of data. When a large block of contiguous data is read from flash memory in a burst, however, the accumulated wait states can have a significant performance impact, even if wait states are incurred only once every page of data.
Synchronous memories have been developed that significantly improve performance by eliminating the step of opening a new page of data using a speculative read mode or by interleaving page read operations. These memories provide the ability to open a page of data in the memory with the use of a controller in response to a data request. However, these memories continue reading from the page with an invalid address until a second read request occurs.
A system and apparatus for controlling a burst sequence in a synchronous memory is described. In one embodiment, the system comprises a synchronous memory and a burst read device coupled to the synchronous memory. In one embodiment, the burst read device is configured to sense a page of data as a current page from the synchronous memory, wherein the current page contains a fixed number of words of data. The device is further configured to latch the current page of data, and synchronously read the current page of data, one word at a time.
In an alternate embodiment, the burst read device further comprises a wrap-bit. If the wrap-bit is not set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a sequential burst read order. If the wrap-bit is set, the burst read device is configured to latch the current page of data, adjust a word pointer to indicate a next word of data, and repeat latching and adjusting in a non-sequential burst read order.